IEEE standard for SystemVerilog--unified hardware design, specification, and verification language

Abstract: This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document. Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, PLI, programming language interface, SystemVerilog, Verilog, VPI.

שנה

2010

שפה

English

סדרה

IEEE Std

הוצאה

Institute of Electrical and Electronics Engineers

מהדורות

1

עמודים

1247

ISBN

9780738161297

מקור הנתונים: Wikidata