RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA designStuart Sutherland
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design
Stuart Sutherland · 2017
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About the book
xxxi, 453 pages : 23 cm
Book details
- Year
- 2017
- Publisher
- Sutherland HDL
- Editions
- 1
- Pages
- 488
- ISBN
- 9781546776345
Data source: Wikidata
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